Gate-all-around field effect transistors (FETs) offer the ultimate in scaling potential by virtue of offering the best electrostatics of any currently known device geometry. However, a drawback to employing a gate-all-around configuration is the difficulty of fabricating deeply scaled devices starting with nanowires due to the fragility of the nanowires. Thus, most process steps performed after the nanowire has been formed must be carefully tuned to preserve the nanowire.
Additionally, gate-all-around FETs are typically formed using either a gate-first or a gate-last process. In any gate-first process flow, the gate material must be removed from beneath the source/drain region of the device by some undercut method which, using conventional techniques, also results in critical dimension loss of the gate line itself, hurting process and device scalability. In wire-before-gate, gate-first, or replacement gate processes, the nanowire must be suspended using a landing pad region, which hurts layout efficiency.
Thus, techniques that solve the above-described problems associated with gate-all-around FET device fabrication would be desirable.